Micron Technology, Inc., Micron Semiconductor Products, Inc., Micron Technology… v. Netlist, Inc.

N OTE: This disposition is nonprecedential.
United States Court of Appeals
for the Federal Circuit
______________________
MICRON TECHNOLOGY, INC., MICRON
SEMICONDUCTOR PRODUCTS, INC., MICRON
TECHNOLOGY TEXAS, LLC,
Appellants
v.
NETLIST, INC.,
Appellee
______________________
2024-1312, 2024-1313
______________________
Appeals from the United States Patent and Trademark
Office, Patent Trial and Appeal Board in Nos. IPR2022-
00744, IPR2022-00745.
______________________
Decided: February 20, 2026
______________________
MICHAEL R UECKHEIM , Winston & Strawn LLP, Red-
wood City, CA, argued for appellants. Also represented by
J UANC Y AQUIAN, Houston, TX.
WILLIAM MILLIKEN, Sterne Kessler Goldstein & Fox
PLLC, Washington, DC, argued for appellee. Also repre-
sented by RICHARD C RUDO; J ONATHAN M. L INDSAY , Irell &
Manella LLP, Newport Beach, CA; J ASON SHEASBY , HONG
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 2
ANNITA ZHONG, Los Angeles, CA; P HILIP J. WARRICK, Wash-
ington, DC.
______________________
Before D YK, P ROST , and REYNA, Circuit Judges.
REYNA, Circuit Judge.
Micron Technology, Inc., Micron Semiconductor Prod-
ucts, Inc., and Micron Technology Texas, LLC appeal two
final written decisions by the Patent Trial and Appeal
Board, which found that appellants failed to prove certain
claims would have been unpatentable as obvious. We af-
firm.
BACKGROUND
I.
Appellee Netlist, Inc. (“Netlist”) owns U.S. Patent
No. 10,489,314 (“’314 patent”). The ’314 patent is directed
to a “memory module,” which allows a computer to access
and retrieve information needed for processing tasks.
J.A. 1725, ¶17. One exemplary memory module from the
’314 patent is disclosed in Figure 1, reproduced below.
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 3
J.A. 50.1
The memory module 10 (red) includes two “ranks” 32
(green), i.e., rows of memory devices, that communicate
with a logic circuit 40 (blue). The logic circuit, in turn, pro-
cesses data received from and sent to an external memory
controller 20 (yellow) located elsewhere in the computer.
Data signals travel to and from the memory module along
a data bus (i.e., the group of data lines labeled “DQ”).
Relevant here are two aspects of the ’314 patent. The
first is that the ’314 patent requires the ranks to operate
non-concurrently, meaning that only one rank is activated
at a time. To read data from, or write data to, a particular
rank, the rank must be “activated.” J.A. 73, 2:64–66. In
order to activate the rank, the memory controller sends
“chip select signals” to the logic circuit, which in turn sends
corresponding “registered chip select signals” to the ranks.
J.A. 73–74, 2:64–3:3. If a rank receives an “active” regis-
tered chip select signal, the rank will activate. J.A. 81,
18:21–60. Contrastingly, if a rank receives a “non-active”
registered chip select signal, the rank will not activate. Id.
The second is that the ’314 patent discloses a memory
module in which the memory controller communicates data
with the memory module at the same speed that the
memory module communicates data internally with its
ranks. J.A. 79, 14:18–21; J.A. 84, 23:50–55. So, for exam-
ple, as disclosed in one embodiment, in an equivalent time
period, the same amount of data is transmitted from the
ranks to the logic circuit as is transmitted from the memory
module to the memory controller. J.A. 57 (Fig. 7).
Independent claims 1 and 15 are representative.
Claim 1’s preamble recites “[a] memory module operable in
1 This version of Figure 1 was presented in appellee’s
response brief, including the annotations and coloring. Re-
sponse Br. 7.
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 4
a computer system to communicate data with a memory
controller of the computer system at a specified data rate.”
J.A. 93, 42:12–14. Claim 1 goes on to recite that the
memory module comprises:
a plurality of memory integrated circuits . . . ,
wherein the plurality of N-bit wide ranks include a
first rank configured to receive or output the first
burst of N-bit wide data signals and the first burst
of data strobes at the specified data rate in response
to the first memory command, and a second rank
configured to receive or output the second burst of
N-bit wide data signals and the second burst of
data strobes at the specified data rate in response
to the second memory command . . . .
J.A. 93, 42:28–38 (emphases added). Relevant here, the
preamble requires that the memory module communicate
data with a memory controller at “a specified data rate.”
Then, the body of the claim requires that the memory mod-
ule’s logic enables circuitry to communicate data with the
ranks at “the specified data rate.”
Claim 15 recites a memory module comprising:
[15.3] logic . . . configured to receive a first set of
input address and control signals associated with a
first read or write memory command and to output
a first set of registered address and control signals
in response to the first set of input address and con-
trol signals,
[15.4] the first set of input address and control sig-
nals including a first plurality of input chip select
signals,
[15.5] the first set of registered address and control
signals including a first plurality of registered chip
select signals corresponding to respective ones of
the first plurality of input chip select signals,
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 5
[15.6] the first plurality of registered chip select
signals including a first registered chip select sig-
nal having an active signal value and one or more
other registered chip select signals each having a
non-active signal value;
[15.7] memory devices . . . arranged in a plurality
of N-bit wide ranks, wherein the plurality of N-bit
wide ranks are configured to receive respective
ones of the first plurality of registered chip select
signals, wherein a first N-bit wide rank in the plu-
rality of N-bit wide ranks receiving the first regis-
tered chip select signal having the active signal
value is configured to receive or output a first burst
of N-bit wide data signals and a first burst of data
strobes associated with the first read or write com-
mand . . . .
J.A. 94–95, 44:47–45:14.2
II.
Micron filed two inter partes review (“IPR”) petitions
challenging certain claims of the ’314 patent as obvious
over prior art reference “Halbert,” and other prior art ref-
erences not at issue on appeal.3
A.
In the first proceeding, IPR2022-00744 (“-744 IPR Pro-
ceeding”), Micron challenged independent claim 1 and cer-
tain of its dependents (claims 2–3, 5, 6, 8–10, and 12–14).
J.A. 9–13. Concerning independent claim 1, the Board de-
termined that Micron failed to show that Halbert would
2 The limitation numbering [15.3]–[15.7] follows the
numbering used by the parties both before the Board and
on appeal.
3 Halbert is a patent application directed to memory
modules. J.A. 1328–45.
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 6
have rendered obvious claim 1’s “specified data rate” limi-
tations. J.A. 9–14. Underlying this determination was the
Board’s construction of “specified data rate.” J.A. 6–9.
Before the Board, both parties agreed that claim 1’s
preamble of “a specified data rate” is limiting and provides
an antecedent basis for the “the specified data rate” recited
in the body of the claim. J.A. 7. Specifically, the preamble
recites a “memory module operable in a computer system
to communicate data with a memory controller of the com-
puter system at a specified data rate.” J.A. 93, 42:12–14
(emphasis added). The body of claim 1, in relevant part,
recites ranks “configured to receive . . . data . . . at the spec-
ified data rate.” J.A. 93, 42:30–33 (emphasis added). Thus,
the Board concluded that later recitations of “the specified
data rate” in claim 1 refer to the “same data rate as ‘a spec-
ified data rate’ in the preamble, which is the rate at which
data are communicated between the memory module and
the memory controller.” J.A. 8.
Applying this construction, the Board determined that
Micron failed to show that Halbert teaches that its ranks
communicate data at the same rate at which data is com-
municated between the memory module and the memory
controller. J.A. 13. The Board found that (1) Halbert’s
ranks communicate one piece of data over one clock cycle
(1:1) and (2) Halbert’s memory module communicates two
pieces of data over one clock cycle (2:1). J.A. 12. In other
words, the Board found that Halbert’s ranks operate at half
the rate as data communicated by the memory module.
J.A. 10–11. This configuration is illustrated below in Hal-
bert’s Figure 4, with ranks (140 and 142) each communi-
cating one piece of data over a clock cycle, and with the
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 7
memory module communicating to the module controller
(110) two pieces of data over a clock cycle.
J.A. 1332.4 Thus, because Halbert’s ranks operate at a dif-
ferent data rate than its memory module, the Board con-
cluded Micron failed to show that Halbert’s ranks teach the
“specified data rate” limitations. J.A. 13. Based on this
determination, the Board upheld the challenged claims.
J.A. 4.
B.
In the second proceeding, IPR2022-00745 (“-745 IPR
Proceeding”), Micron challenged independent claim 15 and
certain of its dependents (claims 16–20 and 22–27), as well
as independent claim 28 and its dependents
(claims 29–33). J.A. 21–33. Concerning independent
claims 15 and 28, the Board noted that Micron relied on the
same arguments for both claims and thus only addressed
4 The red notations displayed in Figure 4 above were
included by Netlist in its briefing before the Board. See
J.A. 1670.
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 8
claim 15. J.A. 22.5 Claim 15 discloses a memory module
with ranks, the ranks of which are “configured to receive”
a “first plurality of registered chip select signals.” J.A. 94–
95, 44:47–45:8. Claim 15 also discloses that “the first plu-
rality of registered chip select signals includ[es] a first reg-
istered chip select signal having an active signal value and
one or more other registered chip select signals each having
a non-active signal value.” J.A. 94–95, 44:65–45:3.
Before the Board, Micron argued that claim 15 was
rendered obvious by the combination of: (1) Halbert’s Fig-
ure 2, an embodiment of ranks with chip select signals that
was prior art to Halbert, and (2) Halbert’s Figure 4, an em-
bodiment of a memory module. J.A. 27–33. The Board de-
termined that Micron failed to show that a skilled artisan
would have been motivated to combine the chip select sig-
nals in Figure 2 with the memory module disclosed in Fig-
ure 4. Id.
The Board acknowledged Micron’s argument that a
skilled artisan would have included Figure 2’s chip select
signals in Figure 4’s memory module. J.A. 27. Specifically,
Micron argued that there was a motivation to do so because
Figure 4’s memory module “is just another design” for the
Figure 2 embodiment, so it would have been obvious to
combine them. J.A. 2386; see also Appellants Br. 42 (not-
ing that both figures had the “same type of . . . memory
module architecture” (citing J.A. 2386)).
The Board rejected this argument. J.A. 27 (noting that
Micron did “not address sufficiently how Halbert’s Figure 4
device would operate with active and non-active chip select
signals, as recited in claim 15” (emphasis added)). As pre-
viously noted, claim 15 requires chip select signals to have
active and non-active signals, as disclosed in limitation
5 On appeal, like below, claim 15 and claim 28 rise
and fall together. Thus, we only address claim 15.
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 9
15.6. See J.A. 94–95, 44:66–45:3. The Board explained
that Micron’s “lack of explanation as to how active and non-
active signals would affect the operation of Halbert’s Fig-
ure 4 device is significant.” J.A. 27. The Board found that
Figure 4’s memory module has concurrently operated
ranks in order to achieve increase throughput. J.A. 30. Ac-
cording to the Board, incorporating Figure 2’s active and
non-active chip signals into Figure 4’s concurrently oper-
ated memory module would result in a slower memory
module, impacting the memory module’s performance.
J.A. 30–31. The Board found that Micron failed to explain
why a skilled artisan would have been motivated to make
the combination, resulting in a non-concurrently operated
memory module, “accounting for the performance impact of
not operating [the] ranks . . . concurrently.” J.A. 31.
The Board then rejected Micron’s additional argument
that its proposed combination rendered claim 15 obvious.
J.A. 31–32. Micron argued Figure 2’s chip select signals
would have been implemented into Figure 4 in a “variety
of well-known and obvious ways,” specifically, that Fig-
ure 2’s chip select signals could have been incorporated
into Figure 4 in order to select data between the ranks for
output to Figure 4’s buffer. Id. The Board rejected this
argument because such a configuration would require the
chip select signals to be sent from Figure 4’s memory con-
troller to its multiplexer, and not from the memory control-
ler to the ranks. And as the Board explained, “[i]f the
active and non-active signals are only used at the [multi-
plexer] and are not sent to the [ranks], then the combina-
tion does not show [ranks] that are ‘configured to receive’”
registered chip select signals, as required by claim 15.
J.A. 32.
Micron appeals. We have jurisdiction under 28 U.S.C.
§ 1295(a)(4)(A).
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 10
D ISCUSSION
Micron raises three issues on appeal. First, Micron ar-
gues that in the -744 IPR Proceeding, the Board implicitly
misconstrued “data rate” within the term “specified data
rate.” Second, Micron argues that in the -745 IPR Proceed-
ing, the Board legally erred in its motivation-to-combine
analysis. Finally, Micron argues that in the -745 IPR Pro-
ceeding, the Board misconstrued limitation 15.6. We ad-
dress each argument in turn.
Obviousness is a question of law based on underlying
factual findings, including the “scope and content of the
prior art” and “the presence or absence of a motivation to
combine” references. B/E Aerospace, Inc. v. C&D Zodiac,
Inc., 962 F.3d 1373, 1379 (Fed. Cir. 2020). We review the
Board’s legal determinations de novo and its factual find-
ings for substantial evidence. Corephotonics, Ltd. v. Apple
Inc., 84 F.4th 990, 1001 (Fed. Cir. 2023). We review the
Board’s claim construction based on intrinsic evidence de
novo and subsidiary factual findings based on extrinsic ev-
idence for substantial evidence. Dionex Softron GmbH
v. Agilent Techs., Inc., 56 F.4th 1353, 1358 (Fed. Cir. 2023).
I.
Micron argues that in the -744 IPR Proceeding, the
Board implicitly misconstrued claim 1’s “specified data
rate.” Appellants Br. 29, 32. Specifically, Micron takes is-
sue with the Board’s construction of “data rate” within the
term “specified data rate.” According to Micron, the Board
erroneously construed this term as “a specific unit of meas-
urement—a piece of data per clock cycle.” Appellants
Br. 29, 32. But, according to Micron, the plain and ordi-
nary meaning of “data rate” is simply a ratio of two things.
Oral argument 4:55–5:08 (“Rate just means ratio, rate
means per, rate does not mean per clock cycle.”). Thus, un-
der this broad meaning, Micron argues Halbert discloses
two ratios which meet the “specified data rate” limitation.
Appellants Br. 34. For the following reasons, we reject
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 11
Micron’s position that the Board implicitly misconstrued
“data rate.”
As an initial matter, we need only construe terms to
the extent necessary to resolve the patentability contro-
versy. Voice Tech Corp. v. Unified Pats., LLC, 110 F.4th
1331, 1341 (Fed. Cir. 2024). Thus, for deciding the patent-
ability controversy before us, we need only decide whether
the plain and ordinary meaning of claim 1’s “data rate” is
broad enough to encompass the two ratios proffered by Mi-
cron—a ratio of rates between two pairs of devices and a
ratio of data per strobe cycle. Appellants Br. 34, 36. We
conclude that it is not that broad. These two ratios cannot
be squared with claim 1’s plain language.
As to Micron’s first proffered ratio, Micron argues that
claim 1’s “data rate” encompasses a ratio of two pieces of
data communicated between a memory module and a
memory controller per every one piece of data being com-
municated to and from the ranks. Appellants Br. 34. Not
so. Per the plain language of claim 1, the claimed “data
rate” reflects transmission of data between components and
not a ratio of two rates across different pairs of devices. In
the preamble, claim 1 requires a data rate between the
memory module and the memory controller. J.A. 93,
42:12–14. In the body of the claim, claim 1 requires a spec-
ified data rate between the logic circuit and ranks. J.A. 93,
42:28–34. Thus, in the context of claim 1, a “data rate” re-
fers to a rate at which data is transmitted between compo-
nents, i.e., data transmission between memory module and
memory controller (preamble) and data transmission
within data ranks (body of claim). This understanding of
the claim necessarily excludes Micron’s proffered ratio,
which is merely a ratio of two rates across different pairs
of devices.
As to Micron’s second proffered ratio, Micron argues
that claim 1’s “data rate” encompasses pieces of data per
strobe cycle. Appellants Br. 36. We reject this
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 12
construction. Claim 1 requires ranks to send data strobes,
in addition to other data signals, at “the specified data
rate.” J.A. 93, 42:49–58. Thus, in the context of claim 1,
for the data rate to have meaning, the baseline by which to
measure the “specified data rate” for data strobes cannot
be data strobes themselves. Thus, Micron’s argument that
data per strobe cycle could be a “specified data rate” fails.
In sum, we reject Micron’s argument that the Board
implicitly misconstrued claim 1’s “specified data rate.”
II.
Micron next argues that the Board’s motivation-to-
combine analysis in the -745 IPR Proceeding was legally
flawed in two respects.
A.
Micron argues that the Board legally erred because it
required Micron to demonstrate a motivation to combine
prior art to arrive at claim limitation 15.6, as opposed to
claim 15 as a whole. Appellants Br. 40–43. Specifically,
Micron argues it was error for the Board to find no motiva-
tion to combine Halbert’s Figures 2 and 4 to arrive at claim
limitation 15.6 when Micron already established a motiva-
tion to combine these two figures for claim limitations 15.4
and 15.5. Id. Micron’s argument, however, rests on a mis-
characterization of the Board’s decision.
Micron never established, nor did the Board find, that
there was a motivation to combine Figures 2 and 4 for claim
limitations 15.4 and 15.5.6 Rather, the Board determined
6 Micron cites to the Board’s final written decision as
purporting to show that the Board agreed with its argu-
ments that there was a motivation to combine Figures 2
and 4 to arrive at claim limitations 15.4 and 15.5. Appel-
lants Br. at 41–42 (citing J.A. 23–25). These pages cited,
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 13
that Micron failed to show a motivation to combine Fig-
ures 2 and 4 to arrive at the “claimed invention,” which re-
quires a memory module with ranks that are configured to
receive active and non-active chip signals. J.A. 31. Thus,
contrary to Micron, the Board did not look at claim limita-
tion 15.6 in isolation but rather considered its require-
ments for active and non-active chip signals in the context
of “the subject matter as a whole, not separate pieces of the
claim.” Sanofi-Synthelabo v. Apotex, Inc., 550 F.3d 1075,
1086 (Fed. Cir. 2008) (citing KSR Int’l Co. v. Teleflex Inc.,
550 U.S. 398 (2007)).
B.
Micron argues that it was legal error for the Board to
require it show a motivation to combine Figures 2 and 4 to
operate in a concurrent operation when it was “undisputed”
that Halbert disclosed a memory module that operates non-
concurrently. Appellants Br. 46. We are not persuaded.
First, as an initial matter, Micron mischaracterizes the
record. The Board did not find that Halbert discloses non-
concurrently run memory modules but rather acknowl-
edged that one statement in Halbert “suggests that the
memory need not be limited to concurrently-operating
ranks.” J.A. 30 (quoting J.A. 1341 ¶30 (emphasis added)).
Second, even considering that Halbert suggests non-
concurrently run memory modules, Micron fails to identify
legal error in the Board’s decision. Here, Micron rested its
motivation-to-combine argument on a combination of Hal-
bert’s Figures 2 and 4. Considering this, the Board found
that Halbert’s Figure 4, the embodiment that Micron relied
on as disclosing claim 15’s memory module, operated with
concurrently run ranks for the purpose of achieving in-
creased throughput. J.A. 29. The Board then found
however, are simply the Board’s summary of Micron’s ar-
guments as to claim limitations 15.4 and 15.5. J.A. 23–25.
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 14
fundamental differences between Figures 2 and 4, namely,
that Figure 2’s chip select signals would “eliminate[]” Fig-
ure 4’s goal of operating concurrently to increase memory
throughput. J.A. 30. The Board then concluded that Mi-
cron failed to address these differences when arguing that
a skilled artisan would be motivated to combine these ref-
erences. J.A. 31. There is no legal error here. “The obvi-
ousness inquiry does not merely ask whether a skilled
artisan could combine the references, but instead asks
whether they would have been motivated to do so.” Adidas
AG v. Nike, Inc., 963 F.3d 1355, 1359 (Fed. Cir. 2020) (cita-
tion modified). Central to the motivation-to-combine in-
quiry is consideration of fundamental differences between
the references. Id. Here, the Board properly considered
the differences between Figures 2 and 4 when assessing
Micron’s motivation-to-combine argument.
III.
Micron argues that in the -745 IPR Proceeding, the
Board erred in construing claim limitation 15.6. Appel-
lants Br. 48–51. Specifically, Micron argues that the Board
required claim 15’s non-active signals to be sent to the
ranks. But, according to Micron, there is no limitation in
the claim as to where non-active signals may be sent. Ap-
pellants Br. 50.
As previously noted, we need only construe terms to the
extent necessary to resolve the patentability controversy.
Voice Tech Corp., 110 F.4th at 1341. Here, there is no need
for us to determine whether claim limitation 15.6 requires
that non-active chip select signals be sent only to the ranks.
No party disputes that claim 15 requires the ranks to re-
ceive active chip select signals. See Appellants Br. 48–50;
Response Br. 64. Micron’s additional motivation-to-com-
bine argument rested on its position that Halbert’s module
controller sent the active chip select signals to the multi-
plexer, and not the ranks. J.A. 31–32. Thus, as the Board
found, Halbert’s active chip select signals are not received
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MICRON TECHNOLOGY , INC. v. NETLIST, INC. 15
by the ranks but rather by the multiplexer, a separate com-
ponent in the memory module. J.A. 32. Micron does not
dispute this finding on appeal. See Appellants Br. 48–52.
As such, Micron’s alternative motivation to combine argu-
ment fails, regardless of whether claim limitation 15.6 re-
quires non-active chip select signals to be sent only to the
ranks.
In sum, we see no error with the Board’s determination
that Micron’s alternative motivation-to-combine argument
fails.
CONCLUSION
We have considered Micron’s remaining arguments
and find them unpersuasive. For the reasons provided, we
affirm.
AFFIRMED
COSTS
Costs for appellee.
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