Pact Xpp Schweiz Ag v. Intel Corporation

N OTE: This disposition is nonprecedential.
United States Court of Appeals
for the Federal Circuit
______________________
PACT XPP SCHWEIZ AG,
Plaintiff-Appellant
v.
INTEL CORPORATION,
Defendant-Appellee
______________________
2025-1419
______________________
Appeal from the United States District Court for the
District of Delaware in No. 1:19-cv-01006-JDW, Judge
Joshua D. Wolson.
______________________
Decided: June 23, 2026
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SANFORD I AN W EISBURST , Quinn Emanuel Urquhart &
Sullivan, LLP, New York, NY, argued for plaintiff-appel-
lant. Also represented by F REDERICK A. L ORIG, R AZMIG
HAGOP MESSERIAN, Los Angeles, CA; Q UINCY L U, Seattle,
WA; MARK YEH -K AI T UNG, Redwood Shores, CA.
J OHN C. O'Q UINN, Kirkland & Ellis LLP, Washington,
DC, argued for defendant-appellee. Also represented by
WILLIAM H. BURGESS , STEPHEN D ESALVO, D IVA R. HOLLIS ,
J ASON M. W ILCOX ; R OBERT ALAN APPLEBY , G REG AROVAS ,
Case: 25-1419 Document: 63 Page: 1 Filed: 06/23/2026

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PACT XPP SCHWEIZ AG v. INTEL CORPORATION 2
T ODD F RIEDMAN, New York, NY; BRANDON BROWN, San
Francisco, CA.
______________________
Before D YK and T ARANTO, Circuit Judges, and MOORE,
District Judge.1
D YK, Circuit Judge.
Appellant PACT XPP Schweiz AG (“PACT”) sued Intel
Corporation (“Intel”) in the United States District Court for
the District of Delaware alleging Intel’s computer-proces-
sor products infringed claims of U.S. Patent Nos. 8,312,301
(“’301 patent”) and 8,471,593 (“’593 patent”). PACT ap-
peals the district court’s summary judgment of nonin-
fringement as to both patents. We affirm.
I
The asserted patents are both directed to processing
architecture in computer systems. The ’301 patent dis-
closes a processor that may selectively change the operat-
ing clock frequencies of its constituent elements. Relevant
to this appeal, representative claim 8 recites “a plurality of
data processing elements adapted for programmably pro-
cessing sequences.” ’301 patent claim 8. The ’593 patent
discloses a multiple-core, multiple-memory processor in
which some cores have a “physically dedicated connection”
to a “physically assigned” memory unit. ’593 patent
claim 1. Representative claim 1 recites “a plurality of data
processing cores . . . wherein . . . each of at least some of the
data processing cores includes a physically dedicated con-
nection to at least one physically assigned one of the plu-
rality of memory units.” ’593 patent claim 1.
1 Honorable K. Michael Moore, District Judge,
United States District Court for the Southern District of
Florida, sitting by designation.
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PACT XPP SCHWEIZ AG v. INTEL CORPORATION 3
PACT sued Intel in district court, alleging that some of
Intel’s multiprocessor computing systems (“accused prod-
ucts”) infringed claims of the ’301 and ’593 patents. The
district court granted summary judgment of noninfringe-
ment as to both patents.
PACT timely appealed, and we have jurisdiction under
28 U.S.C. § 1295(a)(1). We review de novo the district
court’s grant of summary judgment. MobileMedia Ideas
LLC v. Apple Inc., 780 F.3d 1159, 1164 (Fed. Cir. 2015) (cit-
ing Gonzalez v. Sec’y of Dep’t of Homeland Sec., 678 F.3d
254, 257 (3d Cir. 2012)).
II
As to the ’301 patent, the district court construed the
term “sequences” to require sequences of data, rather than
sequences of instructions, based on arguments made by
PACT during a parallel inter partes review proceeding be-
fore the patent office. The district court determined that
there was no dispute that the accused products processed
only sequences of instructions, not data, and concluded
that the products could not infringe. PACT moved for re-
consideration of summary judgment on the ’301 patent, ar-
guing that an accused device may infringe an apparatus
claim if it is capable of infringing. The district court denied
PACT’s reconsideration motion, concluding that PACT
failed to raise a capability-based infringement argument at
summary judgment.
On appeal, PACT argues that the district court erred
in granting summary judgment of noninfringement as to
the ’301 patent. According to PACT, it presented evidence
that the accused products were capable of data processing
and that such capability alone may constitute infringement
of an apparatus claim. See Finjan, Inc. v. Secure Comput.
Corp., 626 F.3d 1197, 1204 (Fed. Cir. 2010); Intel Corp.
v. U.S. Int’l Trade Comm’n, 946 F.2d 821, 832 (Fed. Cir.
1991). We see no error in the district court’s forfeiture de-
termination. In opposing summary judgment, PACT
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PACT XPP SCHWEIZ AG v. INTEL CORPORATION 4
stated only that its expert, Dr. Conte, “has offered evidence
that the Accused Products sequentially processing [sic]
data.” J.A. 14685 (citing J.A. 24308–16 ¶¶ 286–92).2 This
statement does not articulate an infringement theory rely-
ing on capability; instead, PACT argued that Intel’s proces-
sors process data. In his declaration, Dr. Conte opined that
Intel’s “cores can process data in a sequential manner.”
J.A. 24314 ¶ 290. But merely pointing to Dr. Conte’s dec-
laration did not constitute an argument as to capability.
Raising the issue in a reconsideration motion was not suf-
ficient.
PACT concedes that if it failed to raise the capability
argument, Intel would have been entitled to summary
judgment on the ’301 patent. Oral arg. at 4:26–38. Accord-
ingly, we see no error in the district court’s noninfringe-
ment summary judgment as to the ’301 patent.
III
PACT argues that the district court erred in granting
summary judgment of noninfringement as to the ’593 pa-
tent. The district court construed “dedicated connection”
to be “a connection designed to directly interconnect a par-
ticular device to a particular memory via a link inaccessible
to other devices and memories,” based on arguments made
by PACT to distinguish prior art in a parallel ex parte reex-
amination of the ’593 patent. J.A. 43. Determining that
there was no dispute that the core-to-memory pathways in
the accused products were shared with other cores and
memories, the district court granted summary judgment of
noninfringement of the ’593 patent. According to PACT,
the district court incorrectly construed “physically dedi-
cated connection” to effectively require all segments con-
necting a core and its paired memory to exclude use by
2 Citations to “J.A.” refer to the Confidential Joint
Appendix filed by the parties. Dkt. No. 31.
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PACT XPP SCHWEIZ AG v. INTEL CORPORATION 5
other cores or memories. Instead, PACT urges that the
claim limitation is met where “at least one segment in the
end-to-end path” between a core and a memory is “uniquely
devoted” to that pair. Appellant’s Br. 47.
The district court’s construction was correct and is sup-
ported by the prosecution history. During reexamination,
PACT responded to an office action rejecting claim 1 on ob-
viousness grounds by arguing that a “mere direct connec-
tion between two units is not a dedicated connection unless
that connection is specifically devoted to connecting those
two units, and thus not to other units.” J.A. 33956. State-
ments made by a patentee during reexamination inform
claim construction. Presidio Components, Inc. v. Am. Tech.
Ceramics Corp., 875 F.3d 1369, 1379–80 (Fed. Cir. 2017).
PACT’s statement during reexamination supports the dis-
trict court’s construction, “a connection designed to directly
interconnect a particular device to a particular memory via
a link inaccessible to other devices and memories.” J.A. 43.
By contrast, PACT’s proposed construction is inconsistent
with its reexamination statement because if only some of
the physical segments of a connection are “specifically de-
voted,” other physical segments would be shared, and the
connection cannot be said exclude “other units.” See
J.A. 33956.
PACT also argues that, even under the district court’s
adopted construction, there is a genuine dispute of fact con-
cerning where the required “physically dedicated connec-
tion” begins and ends. Appellant’s Br. 51. PACT does not
appear to dispute that the “CoreBo” and “CacheBo,” mod-
ules that provide access to processor cores and memory
units respectively, contain shared lines. Instead, PACT
points to Dr. Conte’s testimony that the CoreBo and
CacheBo are “interfaces.” Id. (citing J.A. 33981 ¶ 172).
However, PACT identifies no evidence that an “interface”
should be considered part of a core or memory and not part
of the core-to-memory connection that must be physically
dedicated.
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PACT XPP SCHWEIZ AG v. INTEL CORPORATION 6
We thus see no error in the district court’s noninfringe-
ment summary judgment as to the ’593 patent.
We have considered PACT’s remaining arguments and
find them unpersuasive.
AFFIRMED
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